Prevention of reverse engineering and data theft is an important consideration at all levels of computer architecture design. To protect their IP investments, designers currently utilize two main approaches to achieve a physically highly secure computing module. Such a “Highly Secure” computing module is suitable for NIST's FIPS 140-2 level 4 certification for cryptographic modules. The first approach to achieve a physically highly secure computing module is to embody the entirety of a function into a single semiconductor chip whose dimensions are so small that it makes physically probing or optically determining secret information infeasible. The second approach to achieve security is to enclose a set of semiconductor devices (such as a CPU, ASIC, FPGA, DRAM, and SRAM) inside a tamper detecting envelope which fully encloses those devices, and which causes all sensitive information in the system to be destroyed upon penetration.
A common problem with building a single chip solution is that often a single chip is too small to fit an entire complex system design in an economic fashion. Additionally, because of the limits of semiconductor process technologies, all of the semiconductor devices that may be needed in the system may not be able to be fabricated in a single semiconductor manufacturing process.
While an enclosed multi-chip solution alleviates some of the problems of the single chip solution, the use of a fully-enclosed envelope introduces a new set of challenges. Often these envelopes (and their associated packaging materials) are highly thermally insulative, and thus limit the amount of power that can be consumed inside the device and transmitted through the envelope as heat. The strict power budget required for such designs often detrimentally impacts the overall performance of the device. Additionally, because the envelope materials must be as sensitive as possible to potential probing attempts, the reliability problems associated with false positive tampers is significant.